1. Field of the Invention
The present invention relates to a clock generating circuit, particularly to a self-modulated type clock generating circuit for spreading the frequency spectrum of an output clock.
2. Description of the Related Art
A conventional clock generating circuit for generating a high-speed clock used in a microprocessor and similar circuits such as a CPU, includes a clock generating circuit that reduces electromagnetic interference (EMI) to peripheral apparatus. One example of such a circuit is a clock circuit disclosed in Japanese Patent Laid-Open No. 235862/1995. The Japanese Patent Laid-Open No. 235862/1995, as shown in FIG. 6, includes a clock modulation circuit 41 for controlling a divider 42. Divider 42 is for dividing an oscillation signal of a voltage controlled oscillator 39 included in a PLL (Phase Locked Loop). The clock modulation is done using an outside reference signal from a quartz oscillation circuit 33. By applying modulation of a low frequency to the clock, power of the clock is not concentrated on a specific single frequency but is spread to a certain constant frequency band to thereby provide an EMI reduction effect. Numeral 35 designates a reference divider for dividing the reference signal of the quartz oscillation circuit 33 and numeral 37 designates a phase frequency comparator for comparing phases of the output of the reference divider 35 and the output of the divider 42. Numeral 38 designates a filter, numeral 41 designates a clock modulation circuit for controlling the divider 42 and numeral 40 designates a buffer for outputting the clock to outside the circuit.
Generally, a PLL circuit receives an external reference signal. The PLL circuit has a voltage controlled oscillator and dividers to divide the reference signal and the oscillation signal from voltage controlled oscillator. Both signals are set to a common frequency referred to as a comparison frequency. An error signal is generated by comparing phases and frequencies of two divided signals. The error signal constitutes a frequency correction signal supplied to the voltage controlled oscillator. The error signal is filtered using a low pass filter referred to as a loop filter before being provided to the voltage controlled oscillator for maintaining the output of the voltage controlled oscillator continuously at a predetermined frequency to generate a high speed clock. The voltage controlled oscillator must continue oscillating without further correction between successive phase frequency comparisons. The longer the period between successive phase frequency comparisons, the wider the deviation becomes from the reference. Therefore, the higher the comparison frequency, i.e., the faster the correction of the voltage controlled oscillator is carried out, the smaller the error and the smaller the correction signal. Conversely, the lower the comparison frequency, the larger the correction signal.
Further, it is known that the main cause of an instantaneous jump phenomenon of the clock frequency which is referred to as cycle-to-cycle jitter of the clock, is a remaining component of the error signal after passing through the loop filter. Therefore, in order to restrain the cycle-to-cycle jitter, it is important to increase the comparison frequency and apply correction before the error is increased.
However, according to the above-described conventional clock generating circuit, the external reference signal is used as the internal clock for operating the clock modulation circuit. In a conventional clock generating circuit for generating a highspeed clock, the frequency of the reference signal is relatively low and a number of clocks generated between successive phase frequency comparisons is small. Therefore, in order to ensure a sufficient number of clock cycles for finishing the processing by the clock modulation circuit prior to the next successive phase frequency comparison, the comparison frequency must be reduced. As a result, the error signal is increased and the cycle-to-cycle jitter is increased.
Further, there has been reported a clock generator for executing fraction division which cannot be dealt with by a divider in a PLL. Such a clock generator uses a xcex94xcexa3 modulator of second order or higher to generate a fixed clock having no modulation. In this case, in order for the xcex94xcexa3 modulator to reproduce a direct current signal having high resolution, a xcex94xcexa3 modulator of second order or higher having noise random performance must be used. As is well known, the xcex94xcexa3 modulator has a noise shaping effect and is operated at ⅙ of an operational frequency or lower to reduce noise and operated at higher than ⅙ of the operational frequency to increase noise. The higher the order of the xcex94xcexa3 modulator, the more increased is the noise at high frequency, i.e., the quantization noise and accordingly, by applying the noise to the PLL, the cycle-to-cycle jitter is increased.
A problem is presented by the conventional systems applying the clock modulation system to a general 2nd order PLL. In the 2nd order PLL system, a loop filter is constituted by series connection of a first capacitor and a first resistor to the ground. The first capacitor has a capacitance value of CL. RL designates a resistance value of the first resistor. It is the common practice to connect an additional capacitor having a capacitance value Cadd sufficiently smaller than the capacitance value CL of the first capacitor (for example, one fiftieth) in parallel with the loop filter. With the additional capacitor (value Cadd) the system approximates a 2nd order PLL system. Here, it is an absolute condition for guaranteeing the stability of the system that the additional capacitor be sufficiently smaller than the first capacitor. That is, the maximum value of phase margin, constituting an index of the stability of the 2nd order PLL, is represented as follows by a ratio of the first capacitor to the additional capacitor:
Phase margin=|tanxe2x88x921(X/xcex3)xe2x88x92tanxe2x88x921(x)|xe2x80x83xe2x80x83(1)
where xcex3xe2x89xa1(CL /Cadd ), Xxe2x89xa1xcfx89xcfx841, xcfx841xe2x89xa1RLxc2x7CL.
Now, consider a case in which the ratio of the first capacitor and the additional capacitor is 1. When the ratio of the first capacitor and the additional capacitor is 1, the maximum possible phase margin becomes zero and such a system cannot be stable. Further, band xcfx893 dB of the system that uses the additional capacitor and approximates a 2nd order PLL is represented by the following:
xcfx893 dB=xcfx89nxc2x7(xe2x88x92(2xcex6231 1)+((2xcex62xe2x88x921)2+1))xe2x80x83xe2x80x83(2)
where xcfx89n=(Koxc2x7Ip/2xcfx80N Cadd), xcex6=xc2xdxcfx89nxcfx842, notation Ko designates a gain of the voltage controlled oscillator, notation Ip designates a current value of a charge pump, notation N designates a number of divisions performed by the divider, and xcfx842=RLxc2x7Cadd. These notations apply to the following description.
Almost all of various parameters determining Equation (2) are normally determined by a desired output clock frequency of the clock generating circuit, and Cadd and RL remain as adjustable parameters. Varying Cadd can change xcfx89n and xcex6, whereas varying RL can only change xcex6. Therefore, the band xcfx893 dB can be adjusted by changing on via adjusting Cadd while maintaining constant xcex6 by adjusting RL such that everything inside of the root sign of Equation 2 is maintained constant. However, as described above, Cadd is permitted to change relative to CL only in a small range. Accordingly, even when the xcex94xcexa3 modulation method is intended to apply to the 2nd order PLL, a PLL band sufficient for removing high-frequency noise generated by the xcex94xcexa3 modulator cannot be ensured.
The present invention includes a 2nd order PLL having a loop filter constituted by series connection of a first capacitor and a first resistor to the ground. The PLL of the present invention also includes a clock modulating circuit controlled by a signal obtained by dividing a signal from a high-speed voltage controlled oscillator. The output of the clock modulating circuit is used to recurrently control the divider. This allows the comparison frequency to be maintained high by guaranteeing a number of clock cycles sufficient for the clock modulating circuit to finish processing are provided during a time period between successive phase frequency comparisons. The reduction of the time period between successive phase frequency comparisons results in smaller correction signals which in turn results in cycle-to-cycle jitter being minimized. Generation of high frequency noise causing the cycle-to-cycle jitter is minimized by using a 1st order xcex94xcexa3 modulator as the clock modulation circuit. The system of the present invention includes a second capacitor having a capacitance value of about {fraction (1/10)} or more of that of the first capacitor in parallel with the loop filter. This effectively removes high frequency noise generated by the xcex94xcexa3 modulator.
One embodiment of the invention includes a self-modulated type clock generating circuit having a 2nd order PLL including a voltage controlled oscillator for generating an external clock signal having a frequency in accordance with an output of a loop filter. The embodiment further includes a divider for dividing the output of the voltage controlled oscillator, converting means for converting an output reference signal into a comparison frequency signal having a predetermined frequency, a phase frequency comparator for comparing phases and frequencies of the output signal of the divider and the comparison frequency signal and generating an error signal that corresponds with the phase frequency error. Also included in the embodiment is a charge pump for generating an electric charge corresponding to the error signal. The embodiment further includes the loop filter having a first capacitor and a first resistor connected in series between an output terminal of the charge pump and a specific potential and a second capacitor connected to the 2nd order PLL in order to remove remaining quantization noise provided to the 2nd order PLL by a 1st order xcex94xcexa3 modulator of a clock modulation circuit. The 1st order xcex94xcexa3 modulator is controlled by a signal derived from the output clock signal. The clock modulation circuit including the 1st order xcex94xcexa3 modulator controls the number of divisions performed by the divider and thereby spreads the frequency of the output clock.
Further, it is preferable that the second capacitor is provided with a capacitance value of {fraction (1/10)} or more of the capacitance value of the first capacitor.
Further, it is also preferable that the self-modulated type clock generating circuit be switched to a fixed clock generating circuit, as needed, by controlling the output of the xcex94xcexa3 modulator.
The above and other objects, aspects, features and advantages of the invention will be more readily apparent from the description of the preferred embodiments thereof taken in conjunction with the accompanying drawings and appended claims.